1. Field of the Invention
The present disclosure relates to the field of fabrication of microstructures, such as integrated circuits, and, more particularly, to a technique for controlling alignment accuracy and pattern placement precision during lithography processes in forming and patterning stacked material layers used for fabricating microstructural features.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable carrier materials. These tiny regions of precisely controlled size are generated by patterning the material layer by performing lithography, etch, implantation, deposition, oxidation processes and the like, wherein typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation, anneal processes and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is represented by the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of at least comparable importance, however, is the accuracy with which an image can be positioned on the surface of the substrate. Typically, microstructures, such as integrated circuits, are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure dose and time and development conditions. Furthermore, non-uniformities of the etch processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern of the current material layer to the etched or otherwise defined pattern of the previously formed material layer while photolithographically transferring the image of the photo mask onto the substrate. Several factors contribute to the ability of the imaging system to perfectly overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure, a limited registration capability of the alignment tool and, as a major contribution to alignment errors, imperfections of the exposure tool itself, such as lens distortions, in particular in combination with respective reticle imperfections. The situation becomes even worse when different exposure tools are used for defining subsequent device layers, since then the inherent errors in the exposure system exposure tool/reticle may vary between the different tools and the different reticles. Although the same exposure tool might be used for imaging critical device layers, in practice such restrictions may not allow an efficient overall process flow in a complex manufacturing environment, which typically comprises a plurality of lithography tools and a plurality of reticles for the same device layer. As a result, the dominant criteria for determining the minimum feature size that may finally be obtained are the resolution for creating features in individual substrate layers and the total overlay error to which the above explained factors, in particular the lithographic process, contribute.
Therefore, it is essential to continuously monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer and to continuously determine the overlay accuracy of patterns of material layers that have been successively formed and that have to be aligned to each other. For example, when forming a wiring structure for an integrated circuit, respective metal lines and vias, which connect two stacked metal regions, may have to be aligned to each other with strict process margins, since a significant misalignment may cause a short between actually non-connected lines, thereby possibly creating a fatal device defect.
In overlay metrology, typically two independent structures, that is, one structure in each layer to be printed, are formed by the specified manufacturing processes and the displacement between the centers of symmetry is determined. Frequently, so-called box-in-box marks are used, which are concentrically patterned in each of the layers and are measured in view of their displacement by an independent measurement tool, wherein typically 4-5 positions within one exposure field, preferably located in the field corners, are measured. However, a discrepancy between overlay characteristics within a single die or exposure field and the significantly larger structures of the overlay marks, which are typically located in the scribe line of the substrate, may be observed, thereby rendering measurement data obtained from the target in the scribe line and thus any control strategies based on these measurement results less reliable. Reasons for this discrepancy are imperfections of the lithography tool and in the reticles used for imaging the respective layers, as previously stated, wherein additionally the fine structures, as are typically found within the die, such as gate electrodes, shallow trench isolation (STI) structures and the like, may be imaged in a different manner compared to relatively large structures, which are typically used to form overlay marks. This pattern and size dependent phenomenon of a different degree of overlay is called pattern placement error (PPE).
Thus, modern advanced process control (APC) strategies strive to reduce respective errors on the basis of the measurement results obtained from previously measured substrates, that is, measurement results corresponding to the overlay marks located in the scribe line, in order to feed back the mismatch indicated by the measurement data for reducing the alignment error in the next substrate to be processed. APC controllers may have a predictive behavior, which is typically referred to as model predictive control (MPC), which may be convenient when the amount of available measurement data is restricted due to process requirements. For example, ideally a large number of overlay marks would be placed across the entire exposure field and would be measured to obtain a representative map of the overlay errors. However, this would require significant process time that may not be available under manufacturing conditions. Furthermore, the provision of a corresponding large number of appropriate overlay marks distributed across the entire exposure field, i.e., the reticle, may possibly result in respective design limitations for the actual product patterns. Hence, many conventional APC mechanisms rely on the measurement data obtained from the scribe line marks.
For generating appropriate manipulated values, the measured “overlay” may be separated into individual alignment parameters, such as magnification, translation, substrate rotation reticle rotation, orthogonality and the like. Consequently, a corresponding exposure tool recipe for aligning the image of a reticle with respect to a specified position of the substrate may contain respective manipulated variables that correspond to the overlay parameters specified above. The manipulated variables may represent so-called controller inputs, that is, any process parameters of the lithography tool which may be adjusted by the controller so as to obtain specified values for the above-specified overlay parameters or control variables, such as magnification, x-translation, orthogonality and the like.
However, generating respective “optimized” values for controlling the alignment activity of the exposure tool on the basis of the four corner overlay marks may not be representative for the entire exposure field, due to the reticle imperfections and the lens distortion mismatches between different exposure tools, as explained above. Rather, the optimization with respect to the corner overlay marks may even cause additional placement errors, since the controller adjustments based on the corner measurement results may be superimposed on respective fluctuations within the exposure field, which may have, due to the above-identified reasons, a significantly different behavior, which may therefore even cause an “amplification” of placement errors. Hence, in some conventional strategies, it is proposed to separate the overlay measurement into two tasks: (a) measuring the conventional overlay pattern on products; and (b) measuring in-die patterns having design rule comparable patterns formed on test substrates using corresponding test reticles. Thus, special exposure field internal effects, as pointed out above, may be taken into consideration by these techniques, the errors caused by the product reticle specific imperfections and the complex interaction thereof with the corresponding imaging performance of the specific one of the plurality of exposure tools that is actually used for imaging a specific device layer is not addressed by these techniques.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.